1. Field of the Invention
The present invention relates generally to buffer circuits and more particularly relates to a high speed buffer circuit having a high input impedance and being particularly suited for use in sample and hold circuits.
2. Description of the Prior Art
Generally, in a sample and hold circuit which intermittently samples a voltage signal to be processed and holds the sampled voltage in a capacitor, when the held voltagge which was sampled and held in the capacitor is delivered to a next stage circuit, it is desired that the input impedance of the next stage circuit be made as high as possible. If the input impedance of the next stage circuit is low, upon holding the voltage, the voltage is leaked from the capacitor to the next stage circuit. Thus, sampled and held voltage is lowered and the lowered voltage becomes an error.
To solve such problem, a circuit of current operation system which employs complementary bipolar transistors has been proposed as shown in FIG. 1. As seen in FIG. 1, this conventional circuit includes a main transistor T1 such as an NPN transistor which is connected as an emitter-follower type. The emitter of transistor T1 is connected to a constant current source 1 and the collector thereof is connected to a transistor T2 such as an NPN transistor which is included in a feedback circuit 2. To the base of the main transistor T1 is connected an input terminal 4 to which a sampled voltage from a sampling and holding capacitor 3 is supplied. Also, an output terminal 5 is connected to the emitter of the main transistor T1.
The feedback circuit 2 further includes transistors T3 and T4 connected in series between power source lines 6 and 7, with each of transistors T3 and T4 being a PNP transistor. The bases of transistors T2 and T3 are connected to each other, while the bases of transistor T4 and the main transistor T1 are connected to each other.
With the circuit constructed as shown in FIG. 1, it is assumed that the current amplification factors h.sub.fe of the PNP and NPN transistors are .beta..sub.P and .beta..sub.N. In the feedback circuit 2, when a current I is derived from the emitter of transistor T2, its base current becomes I/.beta..sub.N which is derived from the base of transistor T3. Accordingly, the collector current of transistor T3 becomes I.multidot..beta..sub.P /.beta..sub.N which then flows in the emitter of transistor T4. Therefore, the base current of transistor T4 becomes I.multidot..beta..sub.P /.beta..sub.N .times.1/.beta..sub.P =I/.beta..sub.N which then flows in the base of the main transistor T1 as a feedback current.
When this feedback current flows in the base of the main transistor T1, the emitter current of the transistor T1 becomes I/.beta..sub.N .times..beta..sub.N =I. Thus, the current which flows from the emitter of transistor T2 to the collector of the main transistor T1 becomes equal to the emitter current of transistor T1 so that the circuit is placed in the stable state. This stable state is determined by the constants of the main transistor T1 and the transistors T2 to T4 in the feedback circuit 2 so that when the transistor T1 and the transistors T2 to T4 are formed on an integrated circuit (IC), the current I is determined.
In this stable state, when the sampled voltage V.sub.S of the capacitor 3 is supplied to the base of the main transistor T1, the emitter current I thereof changes in response thereto. This change is positively fed back through the loop of the feedback circuit 2 from the base current I/.beta..sub.N of transistor T2.fwdarw.the collector current of transistor T3.fwdarw.the base current of transistor T4.fwdarw.the emitter current of the main transistor T1 so that the circuit is placed in a new stable state. Thus, the voltage at the emitter of the transistor T1, and accordingly, the output voltage V.sub.0 at terminal 5 is lower, by the base.emitter voltage V.sub.BE of the transistor T1, than the input voltage V.sub.S. Therefore, the output voltage V.sub.0 fluctuates in response to the input voltage V.sub.S and thus the circuitry constructed as shown in FIG. 1 is operated as a buffer circuit. In addition, when the above circuit is operated as a buffer circuit, it is not necessary to derive the base current from the input terminal 4 (namely, the sampling and holding capacitor 3 of the preceding stage) so as to operate the main transistor T1. The foregoing follows from the fact that the base current for operating main transistor T1 is equally supplied thereto from the feedback circuit 2.
Therefore, by the circuit construction shown in FIG. 1, without deriving the current from the input terminal 4, the output voltage V.sub.O which changes in accordance with the input voltage V.sub.S can be obtained. In other words, a buffer circuit having sufficiently high input impedance can be realized.
However, in the circuit constructed as shown in FIG. 1, since the correcting current which is supplied to the base of the main transistor T1 is positively fed back from the feedback circuit 2 on the basis of the collector current of the main transistor T1 (namely, the emitter current of transistor T2), when the level of the input voltage V.sub.S is changed at high speed, there is then a risk that an undesirable unstable operation such as a so-called ringing or the like may occur on the basis of the delay in the operation of the feedback circuit 2.
Moreover, when changes in the input voltage V.sub.S are of large amplitude and occur at high speed, the circuit of FIG. 1 has the disadvantage that the changed waveform of the ouput voltage V.sub.0 becomes different between the leading edge and the trailing edge. In this connection, when the input voltage V.sub.S is raised at high speed by a large amount the emitter current of the main transistor T1 is made to flow greatly in a moment so that the output voltage V.sub.0 rises up without delay. On the other hand, when the input voltage V.sub.S is lowered at high speed and by a large amount until the stray capacity at the emitter of the main transistor T1 is discharged by the current source 1, the main transistor T1 is turned off in an instant so that the output voltage V.sub.0 falls down with significant delay.
If consideration is given to the use of an FET (field effect transistor) in the buffer circuit for the input voltage of large amplitude, a problem arises in manufacturing the FET together with the IC including bipolar transistors.